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WAT 引起的晶圓低良率問題研究

發表時間:2018-02-28? 瀏覽量:1603? 下載量:395
全部作者: 周波,黃其煜,莫保章
作者單位: 上海交通大學電子信息與電氣工程學院;上海華力微電子有限公司
摘 要: 在晶圓制造過程中,部分產品在金屬互連層進行晶圓可接受度測試(wafer acceptance test,WAT)時會導致芯片出現特定圖形的低良率。本文從WAT引起的缺陷、扎針下壓距離(over drive,OD)、不同金屬層測試和芯片金屬層布線方向等方面分析引起CP失效的原因。驗證了CP失效與芯片尺寸和扎針OD呈正相關,但扎針滑動方向與金屬層布線方向垂直時不會引起CP失效,并發現其失效位置與金屬互連層測試的位置一致。通過選擇布線方向合適的金屬層進行WAT可解決此問題,提出了一種通過驗證的解決方案。
關 鍵 詞: 電子技術;晶圓可接受度測試;金屬互連層;低良率;扎針下壓距離
Title: Study on the wafer low yield induced by WAT
Author: ZHOU Bo, HUANG Qiyu, MO Baozhang
Organization: School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University; Shanghai Huali Microelectronics Corporation
Abstract: In the wafer manufacture process, some products are tested by wafer acceptance test (WAT) at the metal interconnection layer, resulting in a low yield of chip with particular figure. In this paper, the root cause of the CP failure is analyzed through the defect induced by WAT, probe over drive (OD), different metal layer tests and metal line routing direction. The results show that the CP failure has positive correlation with chip size and probe OD. It will not cause CP failure when the metal line routing direction is vertical with the probe slide direction. The results also show that the location of CP failure is completely matched with the WAT at metal interconnection layer. We propose a suitable line routing direction metal layer for WAT to solve this problem and provide a solution which has been verified.
Key words: electronic technology; wafer acceptance test (WAT); metal interconnection layer; low yield; probe over drive
發表期數: 2018年2月第4期
引用格式: 周波,黃其煜,莫保章. WAT 引起的晶圓低良率問題研究[J]. 中國科技論文在線精品論文,2018,11(4):387-392.
 
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